Mahesh Kumar, D and Kannusamy, R (2017) An Efficient Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip Flop. International Journal of Applied Engineering Research, 12 (2). pp. 233-237. ISSN 0973-4562

[thumbnail of An Efficient Design of Low Power Sequential Circuit using Shared Flip Flop.pdf] Text
An Efficient Design of Low Power Sequential Circuit using Shared Flip Flop.pdf - Published Version

Download (721kB)


Power consumption plays an important role in any of the
integrated circuit and is listed as one of the most important top
three challenges in the international technology roadmap for
semiconductors. In any type of integrated circuit, clock
distribution network and flip –flop consumes large amount of
power because they make and employ maximum number of
internal transitions. In the clock distribution network, the
clock signal distributes from a common point to all the
elements that needed for the circuit. However this function is
more important to the synchronous system, much attention has
to give to the characteristics of these clock signals. In the
synchronous system, a clock distribution network consumes a
large amount of total power because of the high operation
frequency of highest capacitance. An effective way to reduce
the capacity of clock load is by minimizing the number of
clocked transistor. Clock distribution networks consumes a
large amount of chip power in a low swing differential
capturing flip flop system and also it creates a more number of
clocked transistor. But by using the proposed system, the
clocked paired shared flip flop is used to reduce the number of
local clocked transistors.
Keywords: Low swi

Item Type: Article
Uncontrolled Keywords: Low swing differential capturing flip flop; Clocked transistor; Pass transistor, Transmission gates
Divisions: PSG College of Arts and Science > Department of Electronics
Depositing User: Mr Team Mosys
Date Deposited: 19 Dec 2022 05:46
Last Modified: 19 Dec 2022 05:46

Actions (login required)

View Item
View Item