Mahesh Kumar, D (2019) An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. American Journal of Electrical and Computer Engineering, 3 (1). pp. 38-45. ISSN 2640-0502

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In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic
blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This
technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional
fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output
response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST
structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It
is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high
diagnostic accuracy of the proposed scheme and its time efficiency.

Item Type: Article
Uncontrolled Keywords: Fault Diagnosis, Built-in Self-Test (BIST), Configurable Logic Block (CLB), Field-Programmable Gate Array (FPGA), Testing
Divisions: PSG College of Arts and Science > Department of Electronics
Depositing User: Mr Team Mosys
Date Deposited: 22 Dec 2022 06:41
Last Modified: 22 Dec 2022 06:41

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