Mahesh Kumar, D (2018) An Optimized Design System for Flip-Flop Grouping Using Low Power Clock Gating. Journal of Network Communications and Emerging Technologies, 8 (3). pp. 55-59. ISSN 2395-5317

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Abstract

Power optimization plays the important role in the
recent years. For reducing dynamic power dissipation data driven
clock gating is a popular technique which is used in many
synchronous circuits. Dynamic power management (DPM) is a
design methodology for dynamically reconfiguring systems to
provide the requested services and performance levels with a
minimum number of active components or a minimum load on
such components. Gating is a circuit which can be manually
inserted into the register transfer level (RTL) design. In a
sequential circuit when a logic unit is clock, its underlying
sequential elements will receive the clock signal regardless of
whether or not they will toggle in the next cycle. These flipflops are grouped together so that they share a common clock
enabling signal which will reduce the hardware overhead. The
group size will lead to maximize the power savings. We present a
high-speed wide-range of parallel counter that achieves the high
operating frequencies through a novel pipeline partitioning
methodology using only three simple repeated CMOS-logic. The
look ahead clock gating is integrated into an Electronic Design
Automation with commercial backend design flow, achieving total
power reduction of various types of large-scale state-of-the-art
industrial and academic designs in 40 and 65 manometer process
technologies. The state look-ahead path prepares the counting
path’s next counter state prior to the clock edge such that the
clock edge triggers all modules simultaneously, thus concurrently
updating the count state with a uniform delay at all counting path
modules/stages with respect to the clock edge.

Item Type: Article
Uncontrolled Keywords: Clock gating, Clock networks, Dynamic power Reduction, Multiple bit flip flop.
Divisions: PSG College of Arts and Science > Department of Electronics
Depositing User: Mr Team Mosys
Date Deposited: 22 Dec 2022 05:53
Last Modified: 22 Dec 2022 05:53
URI: http://ir.psgcas.ac.in/id/eprint/1663

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