Mahesh Kumar, D (2019) An Efficient Fault Detection of FPGA Using Low Transition - Random Test Pattern Generation With Light Weighted Code and EX-OR GATE. International Journal of Electronics Engineering, 11 (1). pp. 54-61. ISSN 0973-7383

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Abstract

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic
blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This
technique can uniquely identify any single bridging, open or stuck-at fault in the inter connect as well as any single
functional fault; a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator
and output response analyzer are configured by existing CLBs in FPGAs. Thus, no extra area overhead is needed for the
proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing
low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects.
Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency

Item Type: Article
Uncontrolled Keywords: : Fault diagnosis, Built-in self-test (BIST), Configurable Logic Block (CLB), Field-Programmable Gate Array(FPGA), Testing.
Divisions: PSG College of Arts and Science > Department of Electronics
Depositing User: Mr Team Mosys
Date Deposited: 22 Dec 2022 06:37
Last Modified: 22 Dec 2022 06:37
URI: http://ir.psgcas.ac.in/id/eprint/1665

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